1. Field of the Invention
The present invention relates to telephones, and more particularly, to a data transfer circuit best suited to cordless telephones or the like.
2. Description of the Related Art
In a cordless telephone, command signals indicating requests and parameters are transferred between the base unit and a handset in cases such as when the handset requires connection between them to the base unit for originating call and when the base unit requires a connection to the handset for receiving a call.
FIG. 7 shows an example of the format of such a command signal CMND. Signal CMND comprises a 16-bit sync signal BSYN at the top, and a 16-bit frame sync signal FSYN next. Sync signals BSYN and FSYN have specified bit patterns respectively. Frame sync signal FSYN sent from the handset to the base unit differs in its bit pattern from frame sync signal FSYN sent from the base unit to the handset.
Command signal CMND further comprises a 25-bit system identification code SYID preceded by signal FSYN, a 15-bit error correction code ECC for SYID, and 5-byte 40-bit control code CTRL. System identification code SYID is used for discriminating the local unit from the remote unit. In control code CTRL, the first byte indicates control for the handset and the base unit, and the second to the fifth bytes indicate parameters or data related to the first byte.
When the handset or the base unit receives command signal CMND, whether the identification code SYID included in the command signal CMND matches identification code stored in the local unit is checked. Only if they match, the command signal CMND is determined to be valid. Otherwise, it is determined to be invalid. For simplicity, data ranging from identification code SYID to control code CTRL will be called user data USRD in the following descriptions.
Such a command signal CMND can be obtained, for example, in a transfer circuit shown in FIG. 8.
There are provided three 16-bit memories 11 to 13 (shift registers with serial input and serial output). Bit sync signal BSYN is arranged in memory 11, frame sync signal FSYN for the base unit is arranged in memory 12, and frame sync signal FSYN for the handset is arranged in memory 13.
There is also provided a 16-bit shift register 14 with serial input and parallel outputs, 16-bit buffer memory 15 with parallel inputs and serial output, and a 16-bit shift register 16 with serial input and serial output used for data transfer.
There is also provided a timing generator 19 and switch circuits 17 and 18. The signals output from the timing generator 19 are supplied to the switch circuits 17 and 18 as control signals. Shift clocks SHFT, also generated in the timing generator, are supplied to the memory 11 to 13 and the shift register 16.
When a microcomputer (not shown) sends a signal indicating permission or direction for forming command signal CMND to the timing generator 19, the switch circuit 18 connects the memory 11 to the shift register 16 during period T.sub.1 corresponding to the first 16 clocks of shift clocks SHFT.
Therefore, bit sync signal BSYN stored in the memory 11 is taken out and supplied to the shift register 16 through the switch circuit 18 during the first 16-clock period, T.sub.1.
In the second 16-clock period, T.sub.2, the switch circuit 18 connects the memory 12 to the shift register 16 if this transfer circuit is provided for the base unit, and the switch circuit 18 connects memory 13 to the ship register 16 if the transfer circuit is provided for the handset.
Therefore, frame sync signal FSYN for the base unit stored in the memory 12 or frame sync signal FSYN for the handset stored in the memory 13 is taken out and transferred to the shift register 16 through the switch circuit 18 in the second 16-clock period, T.sub.2. At the same time, bit sync signal BSYN transferred during T.sub.1 is output from the shift register 16 to pin 22 in synchronization with shift clocks SHFT.
During period T.sub.2, the first 16 bits of user data USRD are supplied in series from pin 21 to the shift register 14. Input clock INCK is also supplied from the timing generator 19 to the shift register 14 to load the first 16 bits of user data USRD to the shift register 14.
When the first 16 bits of user data USRD have been loaded into the register 14 in period T.sub.2, the switch circuit 17 is connected as shown in the figure. Latch pulse CLAT is supplied from the timing generator 19 to the memory 15 through the switch circuit 17. The first 16 bits of user data USRD loaded into the register 14 are latched in parallel in the memory 15.
In the third 16-clock period, T.sub.3, the switch circuit 17 is connected to the terminal opposite to the connected terminal shows in the figure. Shift clocks SHFT are supplied to the memory 15 through the switch circuit 17. The switch circuit 18 is connected to the memory 15.
Therefore, the data in the memory 15, that is, the first 16 bits of user data USRD loaded into the memory 15 in period T.sub.2, are transferred to the shift register 16 through the switch circuit 18 in the third 16-clock period, T.sub.3. At the same time, frame sync signal FSYN transferred during T.sub.2 is output from the shift register 16 to pin 22 in synchronization with shift clocks SHFT.
During period T.sub.3, the next 16 bits of user data USRD are supplied in series from pin 21 to the shift register 14. Input clock INCK is also supplied to the shift register 14 from the timing generator 19 to load the these 16 bits of user data USRD into the shift register 14.
When the these 16 bits of user data USRD have been loaded into the register 14 in period T.sub.3, latch pulse ChaT is supplied to the memory 15 through the switch circuit 17. The 16 bits of user data USRD loaded into the register 14 are transferred in parallel to the memory 15 and latched.
In the fourth 16-clock period, T.sub.4, shift clocks SHFT are supplied to the memory 15 through the switch circuit 17. The switch circuit 18 is connected to the memory 15.
Therefore, the data in the memory 15, that is, the 16 bits of user data USRD loaded into the memory 15 in period T.sub.3, are transferred to the shift register 16 through the switch circuit 18 in the fourth 16-clock period, T.sub.4. At the same time, the first 16 bits of user data USRD transferred during T.sub.3 is output from the shift register 16 in synchronization with shift clocks SHFT and taken out from pin 22.
The same operations as those performed in T.sub.3 and T.sub.4 are repeated afterward. When all of user data USRD is taken out from pin 22, the output of one command signal CMND is finished.
As described above, command signal CMND can be output in the transfer circuit shown in FIG. 8.
In the above-described transfer circuit, sync signals BSYN and FSYN are transferred to the memory 11 to 13. Although sync signals BSYN and FSYN are fixed data, these signals have to be set in the memory 11 to 13 every time command signal CMND is sent.